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tda7427 am-fm radio frequency synthesizer and if counter on-chip reference oscillator and programmable if counter vhf input and precounter for fre- quencies up to 290mhz (suitable for dab application) hf input for frequencies up to 64mhz (short wave band) in-lock detector for search/stop station function stand-by mode for low power con- sumption high current source for 0.5ms lock-in time digital port extension with two outputs for flexibility in applica- tion fully programmable by i 2 c bus description the tda7427 is a pll frequency synthesizer with an additional if counting system that per- forms all the functions needed in a complete pll radio tuning system for conventional and high speed rds tuners. the device has dedicated out- puts for in-lock detection and search/stop sta- tion. november 1999 ? switch am/fm precounter :32/33 5 bit prog. cnt 11-21 bit prog cnt switch swm/dir 11 bit prog cnt inlock detector phase comp ref oscillator charge pump - + switch lp1/lp2 14 bit prog cnt timer control i 2 c bus interface test logic port extension fm_in am_in oscin scl sda if_am if_fm vdd2 gndan/gnddig vref lpout vdd1 lp_fm lp_am d95au418b switch swm/dir 16 bit prog cnt power on reset dout3 vdd1 oscout sstop lp_hc dout1/inlock 16 17 5 6 8 9 19 15 10 11 7 12 18 4 20 1 3 2 13 hfref 14 block diagram ordering numbers: tda7427(dip20) TDA7427D (so20) dip20 so20 1/21
absolute maximum ratings symbol parameter value unit v dd1 supply voltage - 0.3 to + 7 v v dd2 supply voltage - 0.3 to + 11 v p tot total power dissipation 300 mw t stg storage temperature - 55 to + 150 o c t amb ambient temperature -40 to + 85 o c thermal data symbol parameter dip20 so20 unit r th j-amb thermal resistance junction-ambient max 100 150 o c/w lp_fm lp_hc lp_am vref oscin dout3 oscout scl sda 1 3 2 4 5 6 7 8 9 sstop dout1/inlock hfref fm_in vdd1 am_in gnd vdd2 lpout 20 19 18 17 16 14 15 13 12 d95au373b if_am 10 if_fm 11 pin connection tda7427 2/21
pin description (tda7427/d) pin symbol description input/output 1 lp_fm filter opamp input, charge pump output (fm mode) 2 lp_hc filter opamp input, charge pump output (high current mode) 3 lp_am filter opamp input, charge pump output (am mode) 4 vref opamp reference voltage 5 oscin oscillator reference clock input 6 oscout oscillator output 7 dout3 open collector output 8 scl i 2 c bus clock input input 9 sda i 2 c bus data i/o input/output 10 if_am if counter input (am mode) analog input 11 if_fm if counter input (fm mode) analog input 12 sstop if counter result output output 13* dout1 digital output push-pull output 13* inlock inlock detector output output 14 hfref hf reference 15 vdd1 positive power supply 5v supply 16 fm_in high frequency input fm analog input 17 am_in high frequency input am analog input 18 gnd analog digital ground supply 19 vdd2 positive power supply 10v supply 20 lpout filter input, change pump output * pin function is userdefined by software tda7427 3/21
electrical characteristics (t amb =25 c; v dd1 = 5v; v dd2 = 10v; f osc = 4mhz; unless other- wise specified). symbol parameter test condition min. typ. max. unit v dd1 supply voltage 4.5 5.0 5.5 v v dd2 supply voltage 9.0 11.0 v i dd1 supply current no output load 2 4 6 ma i dd2 supply current pll locked 1 2 3 ma i dd1 stb supply current standby mode 1 m a rf input (am_in, fm_in) f iam input frequency am vi = 100mv rms sinusoidal 0.5 64 mhz f ifm input frequency fm vi = 100mv rms sinusoidal 30 200 mhz v imin min input voltage am 0.5 to 16mhz range sinusoidal 30 mvrms v imax max input voltage am 0.6 to 16mhz range sinusoidal 600 mvrms v imin min input voltage fm 70 to 120mhz range sinusoidal 30 mvrms v imax max input voltage fm 70 to 120mhz range sinusoidal 600 mvrms z in input impedance fm input 3 4 5 k w z in input impedance am input 3 4 5 k w if counter (if_am, if_fm) f iam input frequency range am vi = 100mv rms 0.400 11 mhz f iam input frequency range fm vi = 100mv rms 10 11 mhz v imin min input voltage am if pin f in = 455khz 30 mvrms v imin min input voltage fm if pin f in = 10.7mhz 30 mvrms v imax max input voltage am if pin f in = 455khz 600 mvrms v imax max input voltage fm if pin f in = 10.7mhz 600 mvrms z in input inpedance fm if pin 3 4 5 k w z in input inpedance am if pin 3 4 5 k w bus interface t j noise suppression time constant on scl, sda input 50 ns f scl scl clock frequency 400 khz t aa scl low to sda data valid 300 ns t buf time the bus must be free for the new transmission 4.7 m s t hd-start start condition hold time 4.0 m s t low clock low period 4.7 m s t high clock high period 4.0 m s t su-sda start condition setup time 4.7 m s t hd-data data input hold time 1 m s t su-data data input setup time 250 ns t r sda & scl rise time 1 m s t f sda & scl full time 0.3 m s t su-stop stop condition setup time 4.7 m s t dh data out time 300 ns tda7427 4/21
electrical characteristics (continued) symbol parameter test condition min. typ. max. unit v il input low voltage 1v v ih input high voltage 3 v i in input current -5 +5 m a v out output voltage sda acknowledge i o = 1.6ma 0.15 0.4 v oscillator t bu build up time f out = 4mhz 100 ms c in internal capacitance 20 pf c out internal capacitance f osc = 4mhz 20 pf z in input impedance f osc = 4mhz 100 k w v in input voltage (for slave mode) f in = 4 to 13mhz (sinus) capacitance coupling 300 v dd mv pp f in max input frequency (for slave mode) v in = 600mv pp (sinus) 30 mhz loop filter (lp_fm, lp_am, lp_hc, lp_out) i in input leakage current (*) v in = gnd; pd out = tristate (1) -1 0.1 1 m a i in input leakage current (*) v in =v dd1 ;pd out = tristate (1) -1 0.1 1 m a v ol output voltage low i out = -0.2ma 0 0.5 v v oh output voltage high i out = 0.2ma 9.5 10 v i out output current sink 10 30 ma i out output current source v out = 0.5 to 9.5v 10 30 ma dout1/sstop (push-pull outputs) v ol output voltage low i out = -0.1ma 0.1 0.2 v v oh output voltage high i out = 0.1ma v dd1 *0.2 4.9 v dout3 (open collector output) i out output leakage current v out = 10v -1 0.1 1 ma v ol output voltage low i out = -1ma 0.2 0.5 v i out output current sink v out = 0.5 to 9.5v 3 5 ma 1) pd = phase detector (*) lp_fm and lp_hc pins only tda7427 5/21
general description this circuit contains a frequency synthesiser and a loop filter for use in fm/am radio tuning sys- tems. only a vco is required to build a complete pll system. for auto search/stop operation an if counter system is available. for fm and sw am application, the counter works in a two-stage configuration. the first stage is a swallow counter with a two modulus (:32/33) precounter. the second stage is an 11-bit pro- grammable counter. for lw and mw application, a 16-bit programma- ble counter is available. the circuit receives the scaling factors for the pro- grammable counters and the values of the refer- ence frequencies via a i 2 c bus interface. the reference frequency is generated by an inter- nal xtal oscillator followed by the reference di- vider. the device can operate with xtal oscilla- tor between 4 and 13mhz either in master mode and in slave mode. the reference and step frequencies are free se- lectable. (xtal frequency divided by an integer value). the outputs signals of the phase detector are switching the programmable current sources. the loop filter integrates their currents to a dc voltage. values of the current sources are programmable by 6 bits also received via the i 2 c bus. to minimize the noise induced by the digital part of the system, a separate power supply supplies the internal loop filter amplifier. the loop gain can be set for different conditions by setting the cur- rent values of the charge/pump generator. if counter system two separate inputs are available for am and fm if signals. the level of integration is adjustable by six different measuring cycle times. the tolerance of the accepted count value is ad- justable, to reach an optimum compromise for search speed and precision of the evaluation. for the fm range the center frequency of the measured count value is adjustable in 32 steps, to get the possibility of fitting the if filter toler- ance. in the am range an if frequency of 448 to 479khz ( 10.684 to 10.715mhz for am up-con- version) with 1khz steps is available. pll frequency synthesizer input amplifiers the signals applied on am and fm inputs are am- plified to get a logic level in order to drive the fre- quency dividers. the typical input impedance for fm and am in- puts is 4k w . msb lsb function subad bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pll charge pump 00h lpin1/2 currh b1 b0 a3 a2 a1 a0 pll counter 01h pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 pll counter 02h pc15 pc14 pc13 pc12 pc11 pc10 pc9 pc8 pll ref counter 03h rc7 rc6 rc5 rc4 rc3 rc2 rc1 rc0 pll ref counter 04h rc15 rc14 rc13 rc12 rc11 rc10 rc9 rc8 pll lock detect 05h ldena inlock d3 d2 d1 d0 pm1 pm0 ifc ref counter 06h irc7 irc6 irc5 irc4 irc3 irc2 irc1 irc0 ifc ref counter 07h ifcm1 ifcm0 irc13 irc12 irc11 irc10 irc9 irc8 ifc control 08h ifena - - - - ew2 ew1 ew0 ifc control 09h ifs2 ifs1 ifs0 cf4 cf3 cf2 cf1 cf0 osc adjust 0ah - - - osc4 osc3 osc2 osc1 osc0 port extension 0bh - - - - - dout3 - dout1 table 1. address organization tda7427 6/21
register name function pc programmable counter for vco frequency rc reference counter pll irc reference counter if ifcm if counter mode selector ew frequency error window if counter ifena enable ifrc cf center frequency if counter ifs sampling time if counter pm stby, fm, am, am swallow mode selector d programmable delay and phase error for lock detector lpin1/2 loop filter input select pllstop pll stop a charge pump high current b charge pump low current ldena lock detector enable currh set current high osc oscillator adjust dout1 push pull output 5v dout3 open collector output inlock lock detector output table 2. control register functions. osc in register r0 ...r15 predivider :r pd am in fm in register pc0 ...pc4 counter a prescaler m/m+1 register pc5 ... p15 counter :b fref fsyn d95au375a dj to charge pump figure 1. fm and am (sw) operation (swallow mode) tda7427 7/21
divider from vco frequency to reference frequency this divider provides a low frequency f syn which phase is compared with the reference frequency f ref . it is controlled by the registers pc0 to pc4 and pc5 to pc15 operating modes four operating modes are available fo pll; they are user programmable with the mode pm regis- ters (see table): pm0 pm1 operating mode 0 0 standby 1 0 am (swallow) 0 1 am (direct) 11 fm - standby mode: in this mode all device func- tions are stopped. this allows low current consumption without loss of information in all registers. the pin lp-out is forced to 0v, and all data registers are set to efh. the os- cillator keeps running. - fm and am (sw) swallow mode (sw): in this mode the fm or am signal is applied to a 32/33 prescaler, which is controlled by a 5 bit divider 'a'.the 5 bit register (pc0 to pc4) controls this divider. in parallel the output of the prescaler is connected to a 11 bit divider 'b'. (pc5 to pc15). f osc = (r+1) ? f ref dividing range calculation : f vco =[33 ? a + (b + 1 - a) ? 32 ] ? f ref f vco = (32 ? b + a + 32) ? f ref important:for correct operationa 32, b a,with a andb variable values of the dividers). - am direct mode: the am signal is applied di- rectly to the 16 bit static divider 'c'. (pc0 to pc15) f osc =(r+1) ? f ref dividing range: f vco =(c+1) ? f ref three state phase comparator the phase comparator generates a phase error signal according to phase difference between f syn and f ref . this phase error signal drives the charge pump current generator (fig. 3) charge pump current generator this stage generates signed pulses of current. the phase error signal decides the duration and polarity of those pulses. the current absolute values are programmable by a0, a1, a2 registers for high current and b0, b1, registers for low current. low noise cmos op-amp an internal voltage divider at pin vref connects the positive input of the low noise op-amp. the charge pump output connects the negative input. this internal amplifier in cooperation with external components can provide an active filter. osc in register rc0 ... rc15 predivider :r phase detector am in fm in register pc0 ... pc15 prescaler :c fref fsyn d95au376a dj to charge pump figure 2. am direct mode operation for sw, mw and lw tda7427 8/21
11-21 bit counter cf-register 3 bit counter 14 bit counter zd ifs-register ifc-register ew-register up/down counter decode sstop ifena if-am if-fm osc d95au377a figure 4. if counter internal block diagram figure 3. phase comparator waveforms tda7427 9/21
the negative input is switchable to three input pins ( lpin 1, lpin 2 and lpin 3) to increase the flexibility in application. this feature allows two separate active filters for different applications a logical o1o in the lpin 1/2 register activates pin lpin 1, otherwise pin lpin 2 is active. while the high current mode is activated lpin 3 is switched on. inlock detector the charge pump can be switched in low current mode either via software or automatically by the inlock detector by setting bit ldena to o1o. the charge pump is forced in low current mode when a phase difference of 10-40 nsec is reached. a phase difference larger then the programmed values will switch the charge pump immediately in the high current mode. programmable delays are available for inlock de- tection. if counter system (am/fm/am - upc modes) the if counter works in modes controlled by ifcm register (see table): ifcm1 ifcm0 function 0 0 not used 0 1 fm mode 1 0 am mode 11 10.7mhz am up conversion mode typical input impedance for if inputs is 4k w . a sample timer to generate the gate signal for the main counter is build with a 14-bit programmable counter to have the possibility to use any crystal oscillator frequency. in fm mode 6.25khz in am mode a 1khz signal is generated. this is followed by an asynchronous divider to generate different sampling times (see fig. 4). intermediate frequency main counter this counter is a 11/21 bits synchronous autore- load down-counter. four bits are programmable to have the possibility for an adjust to the fre- quency of the cf filter. the counter length is automatically adjusted to the chosen sampling time and the counter mode (am, fm, am-upc). at the start the counter will be loaded with a de- fined value which is an equivalent to the divider value (t sample ? f if ). if a correct frequency is applied to the if counter frequency inputs if-am if-fm, at the end of the sampling time the main counter is changing its state from 0 h to 1fffffh. this is detected by a control logic. the frequency range inside which a successful count results is detected is adjustable by bits ew 0,1,2. adjustment of the measurement sequence time the precision of the measurements is adjustable by controlling the discrimination window . this is adjustable by programming the control registers ew0...ew2. the measurement time per cycle is adjustable by setting the register ifs0 - ifs2. adjust of the frequency value the center frequency of the discrimination win- dow is adjustable by the control register ocf0o to ocf4o. (see data byte specification). port extension and additional functions one digital open collector output and one digital push-pull output are available in application mode. this digital ports are controlled by the data bits dout1 and dout3. d95au378 t high t r t low t r scl sda in sda out t su-sta t hd-sta t hd-dat t sd-dat t subtop t txt t aa t dh figure 5. i 2 c bus timing diagram tda7427 10/21
i 2 c bus interface description the tda7427 supports the i 2 c bus protocol. this protocol defines any device that sends data into the bus as a transmitter and the receiving device as the receiver. the device that controls the transfer is the master and the device being con- trolled is the slave. the master always initiates data transfer and provides the clock to transmit or receive operations. data transition data transition on the sda line must only occur when the clock scl is low. sda transitions while scl is high will be interpreted as start or stop condition. start condition a start condition is defined by a high to low transition of the sda line while scl is at a stable high level. this start condition must precede any command and initiate a data transfer onto the bus. the tda7427 continuously monitors the sda and scl lines for a valid start and will not response to any command if this condition has not been met. stop condition a stop condition is defined by a low to high transition of the sda while the scl line is at a stable high level. this condition terminate the communica- tion between the devices and forces the bus interface of the tda7427 into the initial condition. acknowledge indicates a successful data transfer. the transmit- ter will release the bus after sending 8 bit of data. during the 9th clock cycle the receiver will pull the sda line to low level to indicate it has receive the eight bits of data correctly. data transfer during data transfer the tda7427 samples the sda line on the leading edge of the scl clock. therefore, for proper device operation the sda line must be stable during the scl low to high transition. device addressing to start the communication between two devices, the bus master must initiate a start instruction se- quence, followed by an eight bit word correspond- ing to the address of the device it is addressing. the most significant 6 bits of the slave address are the device type identifier. the tda7427 frequency synthesizer device type is fixed as o110001o the next significant bit is used to address a par- ticular device of the previous defined type con- nected to the bus. the state of the hardwired a0 pin defines the state of this address bit. so up to two devices could be connected on the same bus. the last bit of the instruction defines the type of operation to be performed: - when set to o1o, a read operation is selected - when set to o0o, a write operation is selected the chip selection is accomplished by setting the bit of the chip address to the corresponding status of the a0 input. all tda7427 connected to the bus will compare their own hardwired address with the slave ad- 10 m f 100nf 100nf vdd2 15 vdd1 19 +10v +5v am-fm if if_fm 11 if_am 10 10nf 10nf tda7427 13 12 7 14 inlock/dout1 sstop dout3 hfref 8 9 vdd1 scl sda controller 56 oscin oscout 100nf 4 vref 4mhz 3 6.8nf 100k 68nf 27k 6.8nf 1nf 1 2 15k am vco fm vco 16 20 17 10nf 1nf u tun am_in fm_in lpout lp_fm lp_hc lp_am d95au379b 10nf 10 m f 3.9k 100nf 820 w 3.3nf fm:50khz am:1khz figure 6. application with two loop filters tda7427 11/21
dress being transmitted. after this comparison, the tda7427 will generate an oacknowledgeo on the sda line and will per- form either a read or write operation according to the state of r/w bit. write operation following a start condition the master sends a slave address word with the r/w bit set to o0o. the tda7427 will oacknowledgeo after this first transmission and wait for a second word (the word address field). this 8 bit address field provides an access to any of the 8 internal addresses. upon receipt of the word address the tda7427 slave device will re- spond with an oacknowledgeo. at this time, all the following words transmitted to the tda7427 will be considered as data. the internal address will be automatically incremented. after each word re- ceipt the tda7427 will answer with an oacknow- ledgeo. software specification i 2 c protocol the interface protocol comprises: a start condition (s) a chip address byte (the lsb determines read/write transmission) a sub-address byte. a sequence of data (n-bytes + acknowledge) a stop condition (p) chip address msb lsb 11000100 subaddress msb lsb function t3 t2 t1 i a3 a2 a1 a0 0000 charge pump control 0001pll counter 1 (lsb) 0010pll counter 2 (msb) 0011pll reference counter 1 (lsb) 0100pll reference counter 2 (msb) 0101pll lockdetector control and pll mode select 0110ifc reference counter 1 (lsb) 0111ifcreferencecounter2(msb)andifc mode select 1000if counter control 1 1001if counter control 2 1010 oscillator adjust 1011 port extension 0 page mode off 1 page mode enabled t1, t2, t3 used for testing, in application mode they have to be o0o chip address subaddress data 1 to data n msb lsb msb lsb msb lsb s1100010r/w ack t t t i a3 a2 a1 a0 ack data ack p ack = acknowledge s = start p = stop i = auto increment t = used for testing (in application mode they have to be o 0o) max clock speed 400kbits/s tda7427 12/21
data byte specification charge pump control msb lsb function d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 high current = 0ma 0 0 0 1 high current = 0.5ma 0 0 1 0 high current = 1.0ma 0 0 1 1 high current = 1.5ma 0 1 0 0 high current = 2.0ma 0 1 0 1 high current = 2.5ma 0 1 1 0 high current = 3.0ma 0 1 1 1 high current = 3.5ma 1 0 0 0 high current = 4.0ma 1 0 0 1 high current = 4.5ma 1 0 1 0 high current = 5.0ma 1 0 1 1 high current = 5.5ma 1 1 0 0 high current = 6.0ma 1 1 0 1 high current = 6.5ma 1 1 1 0 high current = 7.0ma 1 1 1 1 high current = 7.5ma 0 0 low current = 0 m a 0 1 low current = 50 m a 1 0 low current = 100 m a 1 1 low current = 150 m a 0 select low current 1 select high current 1 select loop filter lp_fm 0 select loop filter lp_am lpin1/2 currh b1 b0 a3 a2 a1 a0 subaddress = 00h pll counter 1 (lsb) msb lsb function d7 d6 d5 d4 d3 d2 d1 d0 00000000lsb=0 00000001lsb=1 00000010lsb=2 11111100lsb=252 11111101lsb=253 11111110lsb=254 11111111lsb=255 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 bit name subaddress = 01h tda7427 13/21
pll counter 2 (msb) msb lsb function d7 d6 d5 d4 d3 d2 d1 d0 00000000msb=0 0 0 0 0 0 0 0 1 msb = 256 0 0 0 0 0 0 1 0 msb = 512 1 1 1 1 1 1 0 0 msb = 64768 1 1 1 1 1 1 0 1 msb = 65024 1 1 1 1 1 1 1 0 msb = 65280 1 1 1 1 1 1 1 1 msb = 65536 pc15 pc14 pc13 pc12 pc11 pc10 pc9 pc8 bit name subddress = 02h swallow mode: fvco/fsyn = lsb + msb + 32 direct mode: fvco/fsyn = lsb + msb + 1 pll reference counter 1 (lsb) msb lsb function d7 d6 d5 d4 d3 d2 d1 d0 00000000lsb=0 00000001lsb=1 00000010lsb=2 1 1 1 1 1 1 0 0 lsb = 252 1 1 1 1 1 1 0 1 lsb = 253 1 1 1 1 1 1 1 0 lsb = 254 1 1 1 1 1 1 1 1 lsb = 255 rc7 rc6 rc5 rc4 rc3 rc2 rc1 rc0 bit name subaddress =03h pll reference counter 2 (msb) msb lsb function d7 d6 d5 d4 d3 d2 d1 d0 00000000msb=0 0 0 0 0 0 0 0 1 msb = 256 0 0 0 0 0 0 1 0 msb = 512 1 1 1 1 1 1 0 0 msb = 64768 1 1 1 1 1 1 0 1 msb = 65024 1 1 1 1 1 1 1 0 msb = 65280 1 1 1 1 1 1 1 1 msb = 65536 rc15 rc14 rc13 rc12 rc11 rc10 rc9 rc8 bit name subddress = 04h f osc /f ref = lsb + msb + 1 tda7427 14/21
lock detector & pll mode control msb lsb function d7 d6 d5 d4 d3 d2 d1 d0 0 0 pll standby mode 0 1 pll am swallow mode 1 0 pll am direct mode 1 1 pll fm mode 0 0 pd phase difference threshold 10ns 0 1 pd phase difference threshold 20ns 1 0 pd phase difference threshold 30ns 1 1 pd phase difference threshold 40ns 0 0 not used in application mode 0 1 activation delay = 4 ? fref 1 0 activation delay = 6 ? fref 1 1 activation delay = 8 ? fref 0 digital output 1 at pin odout1/inlocko 1 inlock information at pin odout1/inlocko 0 no lock detector controlled chargepump 1 lock detector controlled chargepump ldena inlock d3 d2 d1 d0 pm1 pm0 bit name subaddress = 05h if counter reference control 1 (lsb) msb lsb function d7 d6 d5 d4 d3 d2 d1 d0 00000000lsb=0 00000001lsb=1 00000010lsb=2 11111100lsb=252 11111101lsb=253 11111110lsb=254 11111111lsb=255 irc7 irc6 irc5 irc4 irc3 irc2 irc1 irc0 bit name subaddress = 06h tda7427 15/21
if counter reference control 2 (msb) and if counter mode select msb lsb function d7 d6 d5 d4 d3 d2 d1 d0 00000000msb=0 0 0 0 0 0 0 0 1 msb = 256 0 0 0 0 0 0 1 0 msb = 512 1 1 1 1 0 1 msb = 15616 1 1 1 1 1 0 msb = 15872 1 1 1 1 1 1 msb = 16128 0 0 not used in application mode 0 1 if counter fm mode 1 0 if counter am mode 1 1 if counter am 10.7mhz upconversion mode ifcm1 ifcm0 irc13 irc12 irc11 irc10 irc9 irc8 bit name subaddress = 07h fosc/ftim = lsb + msb + 1 if counter control 1 msb lsb function d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 don't use 0 0 1 don't use 011ewdeltaf= 6.25khz (fm); 1khz (am; am-upc) 100ewdeltaf= 12.5khz (fm); 2khz (am; am-upc) 1 0 1 ew delta f = 25khz (fm); 4khz (am; am-upc) 1 1 0 ew delta f = 50hz (fm); 8khz (am; am-upc) 111 ew delta f = 100khz (fm); 16khz (am; am- upc) x x x x don't use 0 if counter disabled / stand by 1 if counter enabled fena fr3 fr2 fr1 fr0 ew2 ew1 ew0 bit name subaddress = 08h tda7427 16/21
if counter control 2 msb lsb function d7 d6 d5 d4 d3 d2 d1 d0 00000 fcenter = 10.60000mhz (fm) 448khz (am) 10.688mhz (am upc) 00001 fcenter = 10.60625mhz (fm) 449khz (am) 10.689mhz (am upc) 00010 fcenter = 10.61250mhz (fm) 450khz (am) 10.690mhz (am upc) 00011 fcenter = 10.61875mhz (fm) 451khz (am) 10.691mhz (am upc) 00100 fcenter = 10.62500mhz (fm) 452khz (am) 10.692mhz (am upc) 00101 fcenter = 10.63125mhz (fm) 453khz (am) 10.693mhz (am upc) 00110 fcenter = 10.63750mhz (fm) 454khz (am) 10.694mhz (am upc) 00111 fcenter = 10.64375mhz (fm) 455khz (am) 10.695mhz (am upc) 01000 fcenter = 10.65000mhz (fm) 456khz (am) 10.696mhz (am upc) 01001 fcenter = 10.65625mhz (fm) 457khz (am) 10.697mhz (am upc) 01010 fcenter = 10.66250mhz (fm) 458khz (am) 10.698mhz (am upc) 01011 fcenter = 10.66875mhz (fm) 459khz (am) 10.699mhz (am upc) 01100 fcenter = 10.67500mhz (fm) 460khz (am) 10.700mhz (am upc) 01101 fcenter = 10.68125mhz (fm) 461khz (am) 10.701mhz (am upc) 01110 fcenter = 10.68750mhz (fm) 462khz (am) 10.702mhz (am upc) 01111 fcenter = 10.69375mhz (fm) 463khz (am) 10.703mhz (am upc) 10000 fcenter = 10.70000mhz (fm) 464khz (am) 10.704mhz (am upc) 10001 fcenter = 10.70625mhz (fm) 465khz (am) 10.705mhz (am upc) 10010 fcenter = 10.71250mhz (fm) 466khz (am) 10.706mhz (am upc) 10011 fcenter = 10.71875mhz (fm) 467khz (am) 10.707mhz (am upc) 10100 fcenter = 10.72500mhz (fm) 468khz (am) 10.708mhz (am upc) 10101 fcenter = 10.73125mhz (fm) 469khz (am) 10.709mhz (am upc) 10110 fcenter = 10.73750mhz (fm) 470khz (am) 10.710mhz (am upc) 10111 fcenter = 10.74375mhz (fm) 471khz (am) 10.711mhz (am upc) 11000 fcenter = 10.75000mhz (fm) 472khz (am) 10.712mhz (am upc) 11001 fcenter = 10.75625mhz (fm) 473khz (am) 10.713mhz (am upc) 11010 fcenter = 10.76250mhz (fm) 474khz (am) 10.714mhz (am upc) 11011 fcenter = 10.76875mhz (fm) 475khz (am) 10.715mhz (am upc) 11100 fcenter = 10.77500mhz (fm) 476khz (am) 10.716mhz (am upc) 11101 fcenter = 10.78125mhz (fm) 477khz (am) 10.717mhz (am upc) 11110 fcenter = 10.78750mhz (fm) 478khz (am) 10.718mhz (am upc) 11111 fcenter = 10.79375mhz (fm) 479khz (am) 10.719mhz (am upc) 1 1 1 tsample = 160 m s (fm mode); 1ms (am; am-upc) 1 1 0 tsample = 320 m s (fm mode); 2ms (am; am-upc) 1 0 1 tsample = 640 m s (fm mode); 4ms (am; am-upc) 1 0 0 tsample = 1.280ms (fm mode); 8ms (am; am-upc) 0 1 1 tsample = 2.560ms (fm mode); 16ms (am; am-upc) 0 1 0 tsample = 5.120ms (fm mode); 32ms (am; am-upc) 0 0 1 tsample = 10.240ms (fm mode); 64ms (am; am-upc) 0 0 0 tsample = 20.480ms (fm mode); 128ms (am; am-upc) ifs2 ifs1 ifs0 cf4 cf3 cf2 cf1 cf0 bit same subaddress = 09h tda7427 17/21
oscillator adjust msb lsb function d7 d6 d5 d4 d3 d2 d1 d0 x x x 0 0 0 0 0 cload 1,2 = 3pf x x x 0 0 0 0 1 cload 1,2 = 4.25pf x x x 0 0 0 1 0 cload 1,2 = 5.5pf x x x 0 0 0 1 1 cload 1,2 = 6.75pf x x x 0 0 1 0 0 cload 1,2 = 8pf x x x 0 0 1 0 1 cload 1,2 = 9.25pf x x x 0 0 1 1 0 cload 1,2 = 10.5pf x x x 0 0 1 1 1 cload 1,2 = 11.75pf x x x 0 1 0 0 0 cload 1,2 = 13pf x x x 0 1 0 0 1 cload 1,2 = 14.25pf x x x 0 1 0 1 0 cload 1,2 = 15.5pf x x x 0 1 0 1 1 cload 1,2 = 16.75pf x x x 0 1 1 0 0 cload 1,2 = 18pf x x x 0 1 1 0 1 cload 1,2 = 19.25pf x x x 0 1 1 1 0 cload 1,2 = 20.5pf x x x 0 1 1 1 1 cload 1,2 = 21.75pf x x x 1 0 0 0 0 cload 1,2 = 23pf x x x 1 0 0 0 1 cload 1,2 = 24.25pf x x x 1 0 0 1 0 cload 1,2 = 25.5pf x x x 1 0 0 1 1 cload 1,2 = 26.75pf x x x 1 0 1 0 0 cload 1,2 = 28pf x x x 1 0 1 0 1 cload 1,2 = 29.25pf x x x 1 0 1 1 0 cload 1,2 = 30.5pf x x x 1 0 1 1 1 cload 1,2 = 31.75pf x x x 1 1 0 0 0 cload 1,2 = 33pf x x x 1 1 0 0 1 cload 1,2 = 34.25pf x x x 1 1 0 1 0 cload 1,2 = 35.5pf x x x 1 1 0 1 1 cload 1,2 = 36.75pf x x x 1 1 1 0 0 cload 1,2 = 38pf x x x 1 1 1 0 1 cload 1,2 = 39.25pf x x x 1 1 1 1 0 cload 1,2 = 40.5pf x x x 1 1 1 1 1 cload 1,2 = 41.75pf - - - osc4 osc3 osc2 osc1 osc0 bit name subaddress = 0ah port extension control msb lsb function d7 d6 d2 d0 0 cmos push-pull dout1 low 1 cmos push-pull dout1 high 0 npn opencollector dout3 inactive 1 npn opencollector dout3 active 0 0 always o0o in application mode - - dout3 dout1 bit name subaddress = 0bh tda7427 18/21
dip20 dim. mm inch min. typ. max. min. typ. max. a1 0.254 0.010 b 1.39 1.65 0.055 0.065 b 0.45 0.018 b1 0.25 0.010 d 25.4 1.000 e 8.5 0.335 e 2.54 0.100 e3 22.86 0.900 f 7.1 0.280 i 3.93 0.155 l 3.3 0.130 z 1.34 0.053 outline and mechanical data tda7427 19/21
11 0 11 20 a e b d e l k h a1 c so20mec hx45 so20 dim. mm inch min. typ. max. min. typ. max. a 2.35 2.65 0.093 0.104 a1 0.1 0.3 0.004 0.012 b 0.33 0.51 0.013 0.020 c 0.23 0.32 0.009 0.013 d 12.6 13 0.496 0.512 e 7.4 7.6 0.291 0.299 e 1.27 0.050 h 10 10.65 0.394 0.419 h 0.25 0.75 0.010 0.030 l 0.4 1.27 0.016 0.050 k0 (min.)8 (max.) outline and mechanical data tda7427 20/21
information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specification mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectronics. the st logo is a registered trademark of stmicroelectronics ? 1999 stmicroelectronics printed in italy all rights reserved stmicroelectronics group of companies australia - brazil - china - finland - france - germany - hong kong - india - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - u.s.a. http://www.st.com tda7427 21/21

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